• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    The present invention relates to a data transmission integrity verification method between a main upstream unit (10a) and a main downstream unit (20a), the method being characterized in that it comprises the implementation of steps of : - Generation by a data processing module (11a) of the main upstream unit (10a) of a first frame (T1) comprising a packet (P1) of data to be transmitted and a cyclic redundancy code (E1) of said packet (P1); Encapsulating the first frame (T1) in a second frame (T2) further comprising a cyclic redundancy code (C1) of the first frame (T1); Encapsulating the cyclic redundancy code (E1) of the packet (P1) in a third frame (T3); - Comparison by the data processing module (11b) of the at least one auxiliary upstream unit (10b) of each of the cyclic redundancy codes (E1) extracted from the first frame (T1) and the third frame (T3) ; and confirming the integrity of the data transmission to the main downstream unit (20a) only if the comparison is positive.
    公开号:FR3029312A1
    申请号:FR1461569
    申请日:2014-11-27
    公开日:2016-06-03
    发明作者:Yann Vandenbaviere；Christophe Tuzi；Olivier Gallay；Sebastien Lhenoret
    申请人:Sagem Defense Securite SA；
    IPC主号:
    专利说明:

    [0001] GENERAL TECHNICAL FIELD The present invention relates to electric flight controls, and in particular to a data transmission integrity verification method between a main upstream unit and a main downstream unit. STATE OF THE ART Electric flight controls are an evolution of traditional mechanical flight controls. The appearance of fast digital computers has enabled an additional stage of computerization of flight controls in which the pilot merely imposes the overall movement of the aircraft and leaves the computer to control the movements of control surfaces required according altitude, speed, etc. Today, there are many "all-digital" planes whose controls are entirely controlled by a computer. So far, very few helicopters are driven by electric flight controls, and none with all-digital electric flight controls. Indeed, the propulsion of a helicopter is much more complex than that of an airplane. The helicopter moves with two rotors, which provide both lift and propulsion. While on the aircraft, these two functions are decoupled (which allows traction on a single axis), the helicopter can not move in one direction, but is still facing six degrees of freedom. Any modification of rotor blade orientation influences both the traction, lift, drag, power and rotational effect of the apparatus on itself, and both rotors must compensate for their respective influences.
    [0002] For the development of such a platform, whether it is based on a triplex or quadruplex architecture (for redundancy), it is necessary to imagine communication links between all the system calculation units 302 93 12 2. performance better than anything currently done. Since the application is very critical (integrity at 1040 and availability at 10-10), these communication links must also necessarily be reliable, secure, and tolerant to harsh environments (especially lightning). In addition, in an avionics system (a fortiori helicopter), the weight is paramount and in particular the weight of wiring. It is therefore important to minimize the number of external links to each calculator. Finally, as the volume of information and the overall performance requirement of the flight control system are constantly increasing, it is necessary that these communication links offer high speeds and low latencies, which the existing offer does not offer. . The most popular computer bus to date is ARINC-429. However, it suffers from a number of faults: its bit rate is clearly insufficient (100 kbits / s, whereas it would take at least 15 Mbits / s), and its resistance to the environment (especially lightning) is bad. . The 1553 bus has the same problems. To remedy these difficulties, it has been proposed the AFDX (Avionics Full DupleX Switched Ethernet) architecture which is a redundant and reliable Ethernet network. The throughput, the environmental compatibility and the reliability are acceptable, but it is particularly expensive and its latency is much worse than that of ARINC-429 It would be desirable to have a data link, reliable, secure, immune to harsh environments (especially lightning and driving susceptibility), requiring no cabling redundancy, at a lower cost than an ARINC-429 link, with data rates of at least 15Mbit / s and latency of less than 50ps, and being compatible with test equipments and trade tuning. SUMMARY OF THE INVENTION According to a first aspect, the present invention thus relates to a method for verifying data transmission integrity between a main upstream unit and a main downstream unit, the method being characterized in that it comprises implementing steps of: (a) generating by a data processing module the main upstream unit of a first frame comprising a data packet to be transmitted and a cyclic redundancy code of said packet, and transmission to an interface module of the main upstream unit; (b) encapsulation by said interface module of the main upstream unit of the first frame in a second frame further comprising a cyclic redundancy code of the first frame; (c) transmitting the second frame to interface modules of the main downstream unit and at least one auxiliary upstream unit; (d) extracting the first frame from the second frame by the interface modules of the main downstream unit and the at least one auxiliary upstream unit; and transmitting to data processing modules of the main downstream unit and the at least one auxiliary upstream unit; (e) Extracting the packet from the first frame by the data processing module of the main downstream unit; and extracting the cyclic redundancy code from the packet by the data processing module of the at least one auxiliary upstream unit; (f) encapsulation by said interface module of the main upstream unit of the cyclic redundancy code of the packet in a third frame; (g) transmitting the third frame to the interface module of the at least one auxiliary upstream unit; (h) extracting the cyclic redundancy code of the packet from the third frame by the interface module of the at least one auxiliary upstream unit; and transmitting to the data processing module the at least one auxiliary upstream unit; (j) comparing by the data processing module the at least one auxiliary upstream unit of each of the cyclic redundancy codes extracted from the first frame and the third frame; and confirming the integrity of the data transmission to the main downstream unit only if the comparison is positive. According to other advantageous and nonlimiting features: step (c) also comprises transmitting the second frame to the interface module of at least one auxiliary downstream unit; step (d) comprises extracting the first frame from the second frame by the interface module of the at least one auxiliary downstream unit and transmitting to a data processing module of the at least one unit auxiliary downstream; and step (e) comprises extracting the packet from the first frame by the data processing module of the at least one auxiliary downstream unit; the method comprises an additional step (j) of transmitting the packet extracted by the data processing module from the at least one auxiliary downstream unit to the data processing module of the main downstream unit; comparing by the data processing module of the main downstream unit of each of the received packets, and confirming the integrity of the data transmission to the main downstream unit only if the comparison is positive; the packet to be transmitted is a first packet, generated by the data processing module of the main downstream unit from control data, the step (e) comprising the extraction of the packet from the first frame by the module; data processing of the at least one auxiliary upstream unit; and the method further comprising generating by the data processing module the at least one auxiliary upstream unit of a second packet from the same control data as the first packet; the comparison by the data processing module of the at least one auxiliary upstream unit of the first packet and the second packet; and confirming the integrity of the data transmission to the main downstream unit only if the comparison is positive - the method comprises implementing steps of: (a) Generating by the data processing module of the at least one auxiliary upstream unit of a fourth frame comprising the second packet and a cyclic redundancy code of said second packet, and transmission to the interface module of the at least one auxiliary upstream unit; (13) Encapsulating by said interface module the at least one auxiliary upstream unit of the fourth frame in a fifth frame further comprising a cyclic redundancy code of the fourth frame; (y) transmitting the fifth frame to the interface modules of the main upstream unit; (Δ) Extracting the fourth frame from the fifth frame by the interface module of the main upstream unit, and transmitting to the data processing module of the main upstream unit; (c) extracting the second packet from the fourth frame by the data processing module of the main upstream unit; () Comparison by the data processing module of the main upstream unit of the first packet and the second packet; and confirming the integrity of the data transmission to the main downstream unit only if the comparison is positive. the second and third frames conform to the High-Level Data Link Control standard; the upstream units and the downstream units are physically connected via a single wired link; said wired link conforms to the RS-485 standard.
    [0003] According to a second aspect, the invention relates to a flight computer comprising a main upstream unit, a main downstream unit and at least one auxiliary upstream unit, the units being configured to implement the method according to the first aspect. According to a third aspect, the invention proposes a flight control system of an aircraft, comprising at least three computers according to the second aspect, the upstream units of the computers receiving flight control data from at least one flight control member. the aircraft, and the downstream units of the computers providing control instructions to at least one actuator of the aircraft. According to other advantageous and nonlimiting features: each upstream unit of a computer is connected to the downstream units of the other computers. According to a fourth and a fifth aspect, the invention relates to a computer program product comprising code instructions for executing a method according to the first aspect of the invention for verifying data transmission integrity between a main upstream unit and a main downstream unit; and computer readable storage means on which a computer program product comprises code instructions for executing a method according to the first aspect of the invention for verifying data transmission integrity between a main upstream unit and a main downstream unit. PRESENTATION OF THE FIGURES Other features and advantages of the present invention will appear on reading the description which follows of a preferred embodiment. This description will be given with reference to the accompanying drawings, in which: FIG. 1 represents a flight control system architecture in which the method according to the invention is implemented; FIG. 2 is a diagram of an exemplary HDLC frame used by the method according to the invention; FIGS. 3a-h illustrate the steps of a data transmission integrity verification aspect of a preferred embodiment of the method according to the invention; FIGS. 4a-f illustrate the steps of an integrity checking aspect of the generated data of a preferred embodiment of the method according to the invention.
    [0004] DETAILED DESCRIPTION The ARINC-429 architecture mentioned above is a standard that describes both an architecture, an electrical interface and a protocol for conveying digital data. It is based on a "simplex" link, that is to say a unidirectional link 1-to-N, which will be tripled or quadrupled (so as to obtain "triplex" or "quadruplex" architectures). Thus, even if N-1 links fail, the system would work.
    [0005] The present method aims to use in a simple and sufficiently secure way physical interfaces and protocols other than those of ARINC429 while maintaining its topology, so as to maintain the advantages of ARINC-429 while improving its performance, in particular in terms of throughput, latency and environmental resistance.
    [0006] With reference to FIG. 1, the present method is implemented in a flight control system (FCS) of an aircraft (in particular a helicopter), comprising one or more FCC computers (redundant) 1 Flight Control Calculator "). Each computer can be seen as a "line" of pilot control transmission to aerodynamic controls, that is to say the various elements of the aircraft that can change its trajectory, driven by actuators. The pilot acts on control members (handle for example) generating flight control data injected by a module 2 (SSU, "Side Stick Unit", that is to say a mini-unit, the latter designating a joystick allowing to actuate the control surfaces of the aircraft) in the lines 1. Figure 1 represents in particular a triplex architecture with a first line 1.1, a second line 1.2, and a third line 1.3. The lines are identical. By "line" is meant an autonomous set of a plurality of interconnected units 10, 20, including at least one "upstream" unit (FCP, "Flight Control Processor") and at least one "downstream" unit 20 ( ACP, "Actuator Control Processor"). Each upstream unit 10 receives as input the flight control data (translating the global movement of the aircraft desired by the pilot) and generates flight control data (reflecting the actions to be implemented at the level of the organs of the aircraft. aircraft) passing through the aircraft. Each downstream unit 20 (remote, situated at the level of the actuators) receives these flight control data and generates control instructions for the actuators so as to actively move the control surfaces (for example increasing the incidence of the blades of the anti-torque rotor if the pilot wants to change the orientation of the helicopter). Within a line, the units 10, 20 are split according to a COM / MON architecture ("COMmand, MONitoring"). In particular, there is a main upstream unit 10a and at least one auxiliary upstream unit 10b. Similarly, it is possible (as shown in FIG. 1 and the following) to find a main downstream unit 20a and at least one auxiliary downstream unit 20b. The main units 10a, 20a are master units, while the auxiliary units 10b, 20b receive copies of the data received by the main units 10a, 20a and used only to monitor and verify the data provided by the main units 10a, 20a. Each unit 10a, 10b, 20a, 20b comprises a data processing module 11a, 11b, 21a, 21b (typically a processor, which implements data processing) and an interface module 12a, 12b, 22a, 22b (Typically an FPGA, Field-Programmable Gate Array, which handles communications with other units). Both modules can be linked by a local communication link.
    [0007] In the remainder of the present description, the example will be taken of a line 1 with four units 10a, 10b, 20a, 20b: a main upstream unit 10a, an auxiliary upstream unit 10b, a main downstream unit 20a, and a unit auxiliary downstream 20b. As will be seen, the lines 1 are specific in that a single physical link (a single wiring) connects the upstream units 10 to the downstream units 20, which significantly reduces the weight and cost. The present method makes it possible, in spite of this unique wiring, to guarantee the integrity of data transmission within a line 1. In other words, it is possible to guarantee with an error rate of less than 1040 that the data transmitted from the main upstream unit 10a to the main downstream unit 20a are valid. It should be noted, as shown in FIG. 1, that it remains possible to provide transverse wiring of one line 1.1, 1.2, 1.3 to another (so as to allow uninterrupted operation of each line 1 even though the wiring inherent to a line would have been physically damaged, for example by firing if the aircraft is military). Even with these crosswires, the number of physical links to be provided remains much lower than in the prior art. The physical interfaces (hardware) within a line 1 are preferably in accordance with the RS-485 standard (whose bit rate can reach several Mbits / s), and advantageously equipped with galvanic isolations that allow it a complete performance at the lightning and electromagnetic incidents (and thus excellent resistance to the environment). Although RS-485 is not dedicated to electrical flight controls, the present method ensures total reliability.
    [0008] The present method makes it possible to ensure that a packet P1 produced by the data processing module 11 a of the main upstream unit 10a is transmitted identically to the module. data processing 21a of the main downstream unit 20a. The aspect of the method which will now be described assumes that the packet P1 is correctly generated by the data processing module 11a (from the flight control data). However, as will be explained below, in an optional embodiment, the method comprises a verification of the integrity of the data generated by the data processing module 11a (and therefore of the packet P1). The protocol used for the data transmission (between upstream and downstream units 20, ie between interface modules 12, 22 - it should be noted that any format can be used for transmissions between the processing module and the interface module within the same unit) is advantageously in accordance with the HDLC standard (High-Level Data Link Control, ISO / IEC 13239: 2002). The unit used is the frame, with a structure as shown in FIG. 2. Each frame is delimited by two identical flags, and includes a data field ("data"). ") From 20 to 32 bytes. The address field is used as a 2-byte message identifier and is equivalent to the ARINC-429 "label". The 1-byte control field is not used. Between two frames there are at least 15 bits of value "1". The frames that will be concerned in the present method are the second frame T2, the third frame T3, and the possible fifth frame T5. The process begins with a step (a) illustrated by Figure 3a of generation by the data processing module 11a of the main upstream unit 10a of a first frame Ti (in any format) comprising a P1 packet of data to be transmitted and a cyclic redundancy code E1 of said packet P1. Thus T1 = P1 + El. The cyclic redundancy code El (commonly called "checksum") of the packet P1 is obtained by a Cyclic Redundancy Code (CRC), in particular by means of a known hashing procedure. Those skilled in the art will be able to implement a 2-byte CRC-16-CCITT. This frame Ti is transmitted in particular via a local communication link to the interface module 12a of the main upstream unit 10a.
    [0009] In a step (b) illustrated in FIG. 3b, this interface module 12a encapsulates the first frame Ti in a second frame T2 (which this time advantageously conforms to the format of FIG. 2 previously described) further comprising a code of cyclic redundancy Cl of the first frame Ti. In other words, the data field of the second frame T2 is composed of the packet 131 and the associated CRC El. The CRC C1 can be of the same type as the CRC El or for example a 4-byte CRC32-IEEE. In a step (c) illustrated in FIG. 3c, the second frame T2 is transmitted (via the wiring) at least to the interface module 22a of the main downstream unit 20a and to the interface module 12b of the upstream unit auxiliary 10b. If there is at least one auxiliary downstream unit 20b (as in the example), the second frame T2 is also transmitted to its interface module 22b. Each interface module 22a, 22b, 12b extracts in a step (d) the first frame Ti from the second frame T2 (by isolating the identifier of the frame and the CRC Cl) and transmits it to the data processing modules 21a , 21b, llb associated. The data processing module 11b of the auxiliary upstream unit 10b then extracts in a step (e) represented by FIG. 3d the cyclic redundancy code E1 of the packet P1, while the data processing module 21a of the Main downstream unit 20a (and possibly the data processing module 21b of an auxiliary downstream unit 20b) extracts the packet 131 from the first frame Ti. It is noted that, paradoxically, the data processing module 11b of the auxiliary upstream unit 10b can ignore the packet 131 and only look at the cyclic redundancy code E1 of the packet 131 (unlike the downstream side), since as we will see this will allow the auxiliary upstream unit 10b to implement the transmission integrity test. The predicate is that insofar as the wiring is unique, if the auxiliary upstream unit 10b has correctly received the cyclic redundancy code E1 of the packet P1, then it can be assumed that this is also the case of the packet P1 since the CRC is an impression of Pi, for all recipients. Indeed, if an error occurs at the time of sending (at the interface module 12a) or before (at the data processing module 11a), then all transmissions of El will be false. Additional tests will however be implemented in embodiments that will be described later. At this stage, illustrated in FIG. 3e, each of the upstream data processing modules 11a, 11b has a version of CRC El. Thus, in a step (f) represented by FIG. 3f, the interface module 12a of the main upstream unit 10a this time encapsulates the cyclic redundancy code E1 of the packet P1 (which is supplied to it by the data processing module). data 11a) in a third frame T3. In other words, the data field of the frame T3 does not contain P1 (and in practice contains only El). This third frame further comprises a cyclic redundancy code C1 'of the cyclic redundancy code E1 of the packet P1 (similarly to the CRC C1). It should be noted that the CRC Cl and CL 'are different since the hashed data are not the same. In a step (g) illustrated in FIG. 3g, the third frame T3 is transmitted (via the wiring) to the interface module 12b of the auxiliary upstream unit 10b (the downstream units 20a, 20b are not addressed) . Similar to what was done in step (d), the interface module 12b extracts in a step (h) the CRC El from the third frame T3 (by isolating the identifier of the frame and the CRC C1 ') and transmits it to the associated data processing module 11b. The latter then has both versions of CRC El (that extracted from the first frame Ti and that extracted from the third frame T3) and can compare them (bit by bit) in a step (i) represented by FIG. 3h. The integrity of the data transmission to the main downstream unit 20a is confirmed only if the comparison is positive, in other words that the two Els are identical, which is a sign that each of the transmissions of the second and third T2 frames T3 went well (otherwise at least one of the two CRCs would be different). At this stage, the data processing module 21a of the main downstream unit 20a can be sure that the packet P1 has been transmitted without error. It should be noted that in the case of at least one auxiliary downstream unit 20b, the method may comprise an additional step (j) for transmitting the packet P1 extracted by the data processing module 21b from the auxiliary downstream unit 20b to the data processing module 21a of the main downstream unit 20a. As in step (i), are compared by the data processing module 11b of the at least one auxiliary upstream unit 10b each of the received packets P1, the integrity of the data transmission to the downstream unit principal 20a being confirmed only if the comparison is positive, in other words that the two P1 are identical, which is a sign that each of the "downstream" desencapsulations of the second frame T2 has proceeded well (if not at least one of the two P1 would be different). Verification of Integrity of Generated Data The steps described above make it possible to ensure that a packet P1 is properly transmitted, but not that this packet P1 is correct. According to a preferred embodiment, the method comprises verification steps (simple or even double) of verifying the integrity of the data generated by the data processing module 11a of the main upstream unit 10a (from control data). . For this, we designate the packet P1 to be transmitted as a first packet, which will be compared with a monitoring packet P2. The method then comprises the generation by the data processing module 11b of the auxiliary upstream unit 10b of the second packet P2 from the same control data as the first packet Pi, as can be seen in FIG. 4a.
    [0010] According to a simple verification, the step (e) mentioned above comprises the extraction of the packet P1 from the first frame Ti by the data processing module 21a of the at least one auxiliary upstream unit 10b (it will be recalled that previously it had It has been described that in step (e) the CRC E1 of the packet P1) is extracted. A new comparison, this time of the first packet P1 and the second packet P2, can be performed by the data processing module 11b of the auxiliary upstream unit 10b. The integrity of the data transmission to the main downstream unit 20a is then confirmed only if the comparison is positive, i.e. P1 and P2 are identical, which means that the transmitted packet P1 is correct. In a preferred embodiment, the method comprises additional steps, illustrated by the figures, to perform a double check of the packet Pi. The steps that will now be described can be done before the steps (a) - (i) evoked. previously, or concomitantly. It should be noted that the packet P1 can be generated twice, so that the integrity of the data generation is checked once and then the integrity of the data transmission is checked again. Preferably, the two tests are nested to save time.
    [0011] In a step (a) (which may be simultaneous with step (a), to which it is similar), illustrated by FIG. 4b, is generated by the data processing module 11b of the auxiliary upstream unit 10b a fourth frame T4 comprising the second packet P2 and a cyclic redundancy code E2 of said second packet P2. So we have T4 = P2 + E2.
    [0012] This frame T4 (which should normally be identical to the first frame Ti) is transmitted to the interface module 12b of the auxiliary upstream unit 10b. In a step (13) (which may be simultaneous with step (b), to which it is similar) illustrated in FIG. 4c, this interface module 12b encapsulates the fourth frame T4 in a fifth frame T5 (which is again advantageously in accordance with the format of FIG. 2 previously described) further comprising a cyclic redundancy code C2 of the fourth frame T4. In other words, the data field of the fifth frame T5 is composed of the packet P2 and the associated CRC E2, and this fifth frame T5 must normally be identical to the second frame T2. In a step (y) (which may be simultaneous with step (c), to which it is similar) illustrated in FIG. 4d, the fifth frame T5 is transmitted (either via the same wiring or a direct connection because all the upstream modules 10 are arranged in proximity) to the interface module 12a of the main upstream unit 10a. The interface module 12a extracts in a step (Ô) (which may be simultaneous with step (d), to which it is similar) the fourth frame T4 from the fifth frame T5 (by isolating the identifier of the frame and the CRC C2) and transmits it to the associated data processing module 11. The data processing module 11a of the main upstream unit 10a then extracts in a step (c) (which may be simultaneous with step (e), to which it is similar) represented by FIG. 4e the second packet P2 since the fourth frame T4. The latter then has both versions of the packet to transmit (the first packet P1 extracted from the first frame Ti and its copy P2 extracted from the fourth frame T4) and can compare them in a step () (which can be simultaneous with the comparison at the level of the data processing module 11b of the auxiliary upstream unit 10b, mentioned above, to which it is similar) represented by FIG. 4f. The integrity of the data transmission to the auxiliary upstream unit 10b is confirmed only if the comparison is positive, in other words that the packet P1 and the packet P2 are identical, which is a sign that the generation of each of these packages (from the same data) went well. At this point, the data processing module 11a of the main upstream unit 10a can be sure that the packet P1 has been generated (and therefore transmitted) without error.
    [0013] FCC calculator and FCS system According to a second aspect, the invention relates to an FCC type 1 flight computer, in other words a "line" comprising a main upstream unit 10a, a main downstream unit 20a and at least one upstream unit. auxiliary 10b (and advantageously at least one auxiliary downstream unit 20b), the units being configured to implement the method according to the first aspect. The units 10a, 10b, 20a, 20b of the same line 1 are physically connected as explained by a single wired link, in particular a wired link complies with the RS-485 standard.
    [0014] According to a third aspect, the invention relates to a flight control system (of the FCS type) of an aircraft (in particular a helicopter), comprising at least three computers 1.1, 1.2, 1.3 according to the second aspect, so as to obtain a 1. The upstream units 10a, 10b of the computers 1.1, 1.2, 1.3 receive flight control data from at least one piloting member of the aircraft (stick, rudder, etc.). and the downstream units 20a, 20b of the computers 1.1, 1.2, 1.3 provide control instructions to at least one actuator of the aircraft (actuators actuating the control surfaces, etc.). Preferably, each upstream unit 10a, 10b of a computer 1.1, 1.2, 1.3 is connected to the downstream units 20a, 20b of the other computers 1.1, 1.2, 1.3 and / or all the upstream units 10a, 10b of the computers 1.1, 1.2 , 1.3 (respectively all the downstream units 20a, 20b of the computers 1.1, 1.2, 1.3) are connected to each other. The aircraft thus comprises the flight control system, the steering members and the actuators. Computer Program Product According to a third and fourth aspect, the invention relates to a computer program product comprising code instructions for execution (in particular on the data processing means 11a, 11b, 21a, 21b units) of the data transmission integrity verification method between a main upstream unit 10a and a main downstream unit 20a, as well as storage means readable by a computer equipment (in particular a memory of the units) on which this unit is located. computer program product.5
    权利要求:
    Claims (13)
    [0001]
    REVENDICATIONS1. A method of verifying data transmission integrity between a main upstream unit (10a) and a main downstream unit (20a), the method being characterized by including the steps of: (a) Generating by a data processing module (11a) of the main upstream unit (10a) of a first frame (Ti) comprising a packet (P1) of data to be transmitted and a cyclic redundancy code (El) of said packet (P1) ), and transmitting to an interface module (12a) of the main upstream unit (10a); (b) Encapsulation by said interface module (12a) of the main upstream unit (10a) of the first frame (Ti) in a second frame (T2) further comprising a cyclic redundancy code (C1) of the first frame (T1); (c) transmitting the second frame (T2) to interface modules (22a, 12b) of the main downstream unit (20a) and at least one auxiliary upstream unit (10b); (d) Extracting the first frame (Ti) from the second frame (T2) by the interface modules (22a, 12b) of the main downstream unit (20a) and the at least one auxiliary upstream unit (10b) ); and transmitting to data processing module (21a, 11b) the main downstream unit (20a) and the at least one auxiliary upstream unit (10b); (e) extracting the packet (P1) from the first frame (Ti) by the data processing module (21a) of the main downstream unit (20a); and retrieving the cyclic redundancy code (El)) from the packet (P1) by the data processing module (21a) of the at least one auxiliary upstream unit (10b); (f) encapsulating by said interface module (12a) the main upstream unit (10a) of the cyclic redundancy code (El)) of the packet (P1) in a third frame (T3); (g) transmitting the third frame at the interface module (12b) of the at least one auxiliary upstream unit (10b); (h) extracting the cyclic redundancy code (El)) from the packet (P1) from the third frame (T3) by the interface module (12b) of the at least one auxiliary upstream unit (10b); and transmitting to the data processing module (11b) the at least one auxiliary upstream unit (10b); (i) Comparison by the data processing module (11b) of the at least one auxiliary upstream unit (10b) of each of the cyclic redundancy codes (El) extracted from the first frame (Ti) and the third frame (T3); and confirming the integrity of the data transmission to the main downstream unit (20a) only if the comparison is positive.
    [0002]
    The method of claim 1, wherein step (c) further comprises transmitting the second frame (T2) to the interface module (22b) of at least one auxiliary downstream unit (20b); step (d) comprises extracting the first frame (Ti) from the second frame (T2) by the interface module (22b) of the at least one auxiliary downstream unit (20b) and transmitting to a data processing module (21b) of the at least one auxiliary downstream unit (20b); and step (e) comprises extracting the packet (P1) from the first frame (Ti) by the data processing module (21b) of the at least one auxiliary downstream unit (20b).
    [0003]
    3. Method according to claim 2, comprising an additional step (j) of transmitting the packet (P1) extracted by the data processing module (21b) from the at least one auxiliary downstream unit (20b) to the processing module of data (21a) of the main downstream unit (20a); for comparing by the data processing module (21a) of the main downstream unit (20a) of each of the received packets (P1), andconfirming the integrity of the data transmission to the main downstream unit (20a) only if the comparison is positive.
    [0004]
    4. Method according to one of the preceding claims, wherein the packet (P1) to be transmitted is a first packet, generated by the data processing module (21a) of the main downstream unit (20a) from data of command, step (e) comprising extracting the packet (P1) from the first frame (Ti) by the data processing module (21a) of the at least one auxiliary upstream unit (10b); and the method further comprising generating by the data processing module (11b) the at least one auxiliary upstream unit (10b) of a second packet (P2) from the same control data as the first packet ( P1); comparing by the data processing module (11b) the at least one auxiliary upstream unit (10b) of the first packet (P1) and the second packet (P2); and confirming the integrity of the data transmission to the main downstream unit (20a) only if the comparison is positive.
    [0005]
    5. Method according to one of the preceding claims, comprising the implementation of steps of: (a) Generation by the data processing module (11b) of the at least one auxiliary upstream unit (10b) of a fourth frame (Ti) comprising the second packet (P2) and a cyclic redundancy code (E2) of said second packet (P2), and transmission to the interface module (12b) of the at least one auxiliary upstream unit (10b) ; (13) Encapsulation by said interface module (12b) of the at least one auxiliary upstream unit (10b) of the fourth frame (T4) in a fifth frame (T5) further comprising a cyclic redundancy code (C2) fourth frame (T4); (y) transmitting the fifth frame (T5) to the interface module (12a) of the main upstream unit (10a); (Ô) extracting the fourth frame (T4) from the fifth frame (T5) by the module interface (12a) of the main upstream unit (10a), and transmission to the data processing module (11a) of the main upstream unit (10a); (c) extracting the second packet (P2) from the fourth frame (T4) by the data processing module (11a) of the main upstream unit (20a); () Comparison by the data processing module (11a) of the main upstream unit (10a) of the first packet (P1) and the second packet (P2); and confirming the integrity of the data transmission to the main downstream unit (20a) only if the comparison is positive.
    [0006]
    6. Method according to one of the preceding claims, wherein the second and third frames (T2, T3) comply with the High-Level Data Link Control (HDLC) standard.
    [0007]
    7. Method according to one of the preceding claims, wherein the upstream units (10a, 10b) and the downstream units (20a, 20b) are physically connected via a single wire link.
    [0008]
    The method of claim 7, wherein said wired link is in accordance with the RS-485 standard.
    [0009]
    Flight calculator (1) comprising a main upstream unit (10a), a main downstream unit (20a) and at least one auxiliary upstream unit (10b), the units being configured to implement the method according to one of the preceding claims.
    [0010]
    10. An aircraft flight control system, comprising at least three computers (1.1, 1.2, 1.3) according to claim 9, the upstream units (10a, 10b) of the computers (1.1, 1.2, 1.3) receiving data from flight control from at least one aircraft steering member, and downstream units (20a, 20b) of the computers (1.1, 1.2, 1.3) providing control instructions to at least one actuator of the aircraft.
    [0011]
    11. The system of claim 10, wherein each upstream unit (10a, 10b) of a computer (1.1, 1.2, 1.3) is connected to the downstream units (20a, 20b) of other computers (1.1, 1.2, 1.3).
    [0012]
    A computer program product comprising code instructions for executing a method according to one of the claims 1 to 8 for verifying data transmission integrity between a main upstream unit (10a) and a downstream unit principal (20a).
    [0013]
    13. Computer-readable storage means on which a computer program product includes code instructions for executing a method according to one of the claims 1 to 8 for verifying data transmission integrity between a main upstream unit (10a) and a main downstream unit (20a).
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    公开号 | 公开日
    US10142059B2|2018-11-27|
    BR112017010865A2|2018-01-09|
    EP3224976A1|2017-10-04|
    EP3224976B1|2019-01-02|
    RU2677454C1|2019-01-16|
    WO2016083494A1|2016-06-02|
    KR101868571B1|2018-06-18|
    US20170324515A1|2017-11-09|
    CN107005348A|2017-08-01|
    KR20170094250A|2017-08-17|
    CN107005348B|2018-04-13|
    FR3029312B1|2016-12-16|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1461569A|FR3029312B1|2014-11-27|2014-11-27|METHOD OF VERIFYING INTEGRITY OF DATA TRANSMISSION BETWEEN A MAIN UPSTREAM UNIT AND A MAIN DOWNSTAIR UNIT|FR1461569A| FR3029312B1|2014-11-27|2014-11-27|METHOD OF VERIFYING INTEGRITY OF DATA TRANSMISSION BETWEEN A MAIN UPSTREAM UNIT AND A MAIN DOWNSTAIR UNIT|
    EP15801778.0A| EP3224976B1|2014-11-27|2015-11-26|Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit|
    BR112017010865-8A| BR112017010865A2|2014-11-27|2015-11-26|data transmission integrity verification process between a main upstream unit and a main downstream unit|
    RU2017122243A| RU2677454C1|2014-11-27|2015-11-26|Method for verifying data transmission continuity between main input unit and main output unit|
    CN201580064717.5A| CN107005348B|2014-11-27|2015-11-26|The method for verifying the integrality of the data transfer between main upstream units and main downstream units|
    PCT/EP2015/077748| WO2016083494A1|2014-11-27|2015-11-26|Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit|
    US15/529,420| US10142059B2|2014-11-27|2015-11-26|Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit|
    KR1020177017411A| KR101868571B1|2014-11-27|2015-11-26|Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit|
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